Our board is a MC68060 (big endian CPU using same interface than MPC860) + PLX9054AC50PI both running at 48 MHz.
PCI running at 33 MHz.
PLX is in M mode.
We connected :
D31-D0 CPU to D0-D31 (M mode) PLX 
A31-A0 CPU to A0-A31 (M mode) PLX
Siz1-0 PCI to TSIZ0-1 PLX
TS CPU connected to TS PLX
RW CPU connected to RW PLX
TA CPU connected to TA PLX
CCS# generated from CPLD during entire bus cycle (we place local registers at $E8000000).
No burst used brom 060 and BI# active on PLX.
  

Several questions after 10 days of trying to solve the big problem... on the last question  ;-)


1-
PLx is used as HOST bridge with no CPU on PCI a no EEPROM : the 060 initializes the PLX --> 8.2K pullup on EEDI/EEDO.
Not clear in the 9054 DB and we needed to read 9056 DB to get a precise info about pull-up in this setting.
Correct ?


2-
RESET the LOCAL part of the PLX
Is the PCIRST# on PCI reseting the complete PLX chip or just PCI part ?
The PCI 2fact25 cycle duration is a requirement for PCI or for all chip ?
We have 33Mhz -> 1s duration hardware reset. Correct ?
We'd like to use the software bit of PLX to reset the PLX, but it seems that this bit is not usable from local CPU : 
when activated, the local interface is out and we cannot go back to erase the bit and leave the reset state.
Please confirm this behaviour.
Actually we OR a CPLD register with CPU bus RESET, the out is connected to PCIRST# PLX.  
Is they a 100% software method to reset the complete PLX from local interface ?? 


3-
After Reset, the PLx local register $8E (PROT_AREA) is $00 and the DB tells that it should be $30 (2 bits are 1 by default).
IS the DataBook correct ? 


4-
BIG & LITTLE endians behaviour.
We put a 8.2K pullup resistor on BIGEND#
Do we need to pullup  or is the pin really internally pulluped.
Whitout pullup I found the pin floating near 0 value and the WAIT# function was not activated, sure.

After Reset we test the following behaviours :
LITTLE
ADD  $03  $02  $01  $00  <---- LITTLE/defaut/as presented on DB.PDF
VAL  $90  $54  $10  $b5  <----       
From CPU, we read byte $90 at add $00
 
BIG (put bit BIG in BIG register)
ADD  $03  $02  $01  $00      
VAL  $90  $54  $10  $b5        
From CPU, we read byte $b5 at add $00

ARE THESE 2 behaviours correct ??  


5-
We initialized the PLX local registers for PCI IO & Config cycles (add $D0000000)
Here are the registers we initialized all with 32 bit accesses :

Values 
0x00300100 => BIGEND, Big/Little Endian Descriptor / Local Miscellaneous Control
0xf0000000 => DMRR, Local Range Register for PCI Initiator-to-PCI
0xd0000000 => DMLBAI, Local Bus Base Address Register for PCI Initiator-to-PCI I/O Config
0x00000000 => DMCFGA
0x00300500 => BIGEND, Big/Little Endian Descriptor / Local Miscellaneous Control
0x00000007 => PCICSR, PCI Command / Status Register
0x00000002 => DMPBAM, PCI Base Address (Remap) Register for PCI Initiator-to-PCI Memory

We have PCI slot with IDSEL=AD21, but nothing connected on.

The PCI configuration Read cycle gives us very strange behavior :

When we send a PCI conf read command (we write value $8000A000 in DMCFGA) we cannot get the vendor ID $FFFF value from the master abort we can see with logic analyser.
And the AD21 line is not set with FRAME#.
We tried to scan all AD lines but there is never a 1 for selecting device.


About Vendor ID we get many different values and after many tests and tries, it seems that the value we get is the last value read on PLX registers ($E80000xx).
We verified with logic analyser and the wee the CPU access and the FRAME# on ADD phase with good C/BE3-0 = 1010. We see the IRDY# on data phase too.

We are now disapointed with this behaviour...
What is the thing we should know and that is no inside the DB ??
Where is the bad thing we did ?
Is it ok to write all registers with 32 bit accesses ?
Or is the PLX defect ??

PLEASE HELP







